1. Field of the Invention
The present invention relates in general to redundancy circuitry for memory devices. In particular, the present invention relates to redundancy circuitry for memory cells in memory devices. More particularly, the present invention relates to redundancy circuitry for memory devices that consumes zero static power.
2. Technical Background
Pursuant to the technological advancements in the fabrication of VLSI memory integrated circuits, the integration density of memory devices is steadily increasing. As the storage capacity per unit area of such memory devices increases, the probability increases that any defects found in the semiconductor during fabrication of such mass memory cells will render a device useless. This directly leads to a decrease of the manufacturing yield rate. To circumvent this yield rate decrease problem associated with the fabrication of large capacity memory devices, on-chip redundant memory cells and their control logic have been proposed. Redundant memory cells and the associated control logic serve to replace defective memory cells found in the semiconductor, so that devices with a limited number of defective memory cells can still be used as qualified memory devices, salvaging the device from otherwise being disposed of.
Reference is made to two U.S. patents, namely, U.S. Pat. No. 4,748,597 issued May 31, 1988, "Semiconductor Memory Device With Redundant Circuits" by Shozo Saito et al., and U.S. Pat. No. 5,146,429 issued Sep. 8, 1992, "Semiconductor Memory Device Including Redundancy Circuitry for Repairing a Defective Memory Cell and a Method for Repairing a Defective Memory Cell" by Shinji Kawai et al.
FIG. 1 of the accompanying drawings shows a schematic diagram of a prior art redundancy circuitry as an example of a circuit employed to solve a memory device having defective memory cells. The memory redundancy circuitry of FIG. 1 comprises two portions, namely the redundancy activation circuit 10 and the programmable redundancy decoder logic 20. The redundancy activation circuit 10 is control circuitry that selectively activates the decoder logic 20 when a memory device is found to be defective. The redundancy activation circuit 10 includes two fuse elements FE.sub.1 and FE.sub.2, a resistor Z of high impedance, an NMOS transistor NE and two PMOS transistors PE.sub.1 and PE.sub.2. The programmable redundancy decoder logic 20 is composed of an array of, say n, decoder units 22 each of which includes a fuse element F.sub.i (i=1, 2, . . . , n) and an NMOS transistor T.sub.i (i=1, 2, . . . , n). Gate terminals of each of the transistor T.sub.i of the decoders 22 are fed by address signals X.sub.i (i=1, 2, . . . , n) of the memory device in question. As used in the art, a fuse element means a conduction path on the semiconductor that can be deliberately destroyed (blown) by a laser beam in order to configure or program different functions for the semiconductor. In the instant case, the configuration or programming results in a substitution of reserve memory cells for defective ones.
Before the memory redundancy circuitry, as shown in FIG. 1, of a memory device, is selected and activated, the electric potential of node A of the redundancy activation circuit 10 is maintained at a high voltage level (V.sub.CC) due to the presence of the fuse FE.sub.1 being connected to V.sub.CC and resistor Z being of high impedance and connected to the ground potential of the system. On the other hand, the potential of node B of the programmable redundancy decoder logic 20 is maintained at the low level (GND) due to the presence of the series-connected fuse element F.sub.i and transistor T.sub.i of each decoder unit 22, which is connected to the ground potential. In this condition of the device, the potential of the redundancy activation status signal RD outputted from redundancy activation status output stage 25 is maintained at the high level.
When the memory redundancy circuitry of FIG. 1 is selected and activated, so as to replace certain defective main memory cells in the device, all the fuse elements F.sub.i in the programmable redundancy decoder logic 20 are deliberately blown. The fuse elements FE.sub.1 and FE.sub.2 of the redundancy activation circuit 10 are blown as well. In this condition of the device, node A goes to a low signal level, as well as the CE (chip enable) signal. The two PMOS transistors PE.sub.1 and PE.sub.2 go into conduction as a result making node B to go to a high level. When node B is goes to a high level, the redundancy activation status signal RD is driven to a low level, indicating that the operation of the memory device is conducted in the redundant memory cell array, not the main memory cell array. When node B is at a low level, RD maintains its high signal level, indicating that the operation is conducted in the normal memory cell array, not in the redundancy.
However, due to the fact that the memory redundancy circuitry shown in FIG. 1 of the exemplified prior art conserves only the fuse elements of the redundant bits that correspond to those in the normal memory cell array that are defective, all other fuse elements of the redundant bits that correspond to all the good bits are blown. In other words, in most of the occasions, most of the fuse elements in the programmable redundancy decoder logic 20 are required to be blown, because relatively fewer defective memory cells than normal ones are found in the typical memory device. That means, this prior art requires more fuse elements to be blown than those that should be maintained intact. More fuse blowing represents higher possibility of erroneous programming. Some of the fuses may not be completely blown, triggering decoding errors.
Moreover, when the all the memory cells are perfect in the normal, or in other words, in the main memory cell array, then since the memory redundancy circuitry of FIG. 1 need not be activated, all the fuse elements are remained un-blown. That is to say, both fuse elements FE.sub.1 and FE.sub.2 in the redundancy activation circuit 10 and all fuse elements F.sub.i in the programmable redundancy decoder logic 20 are kept intact. This results in currents flowing through the resistor Z and the PMOS transistors PE.sub.1 and PE.sub.2 of the redundancy activation circuit 10, as well as through all the transistors T.sub.i of the programmable redundancy decoder logic 20. This is an obvious waste of power, a penalty to memory devices having no defects in their main memory cell arrays.